1. Field of the Invention
The present invention relates generally to methods of designing electronic circuits. More specifically, but without limitation thereto, the present invention relates to a method of simplifying integrated circuit design flow by introducing appropriate capacitive margins to estimate timing delays.
2. Description of Related Art
In previous methods for designing integrated circuits, several iterations of cell placement, routing and signal analysis of the capacitive effects of the interconnections are typically required to satisfy timing constraints, sometimes requiring weeks of cross-talk analysis after parasitic extraction is performed on the circuit floorplan. Because cross-talk analysis is so time consuming, it presents a significant bottleneck in the design cycle of integrated circuits.
An alternative to the time-consuming process of cross-talk analysis is the use of capacitive margins to estimate delays induced by cross-talk. An example of estimating cross-talk using capacitive margins is disclosed in U.S. Pat. No. 6,810,505 B2 for INTEGRATED CIRCUIT DESIGN FLOW WITH CAPACITIVE MARGIN. The method of delay analysis disclosed in that patent estimates slow-down delays for worst case setup time and speed-up delays for best case hold time.